Conventional complementary metal oxide semiconductor (CMOS) integrated circuits comprise p-type devices and n-type devices formed on the same level in a semiconductor substrate, i.e., the various components of p-type devices are coplanar with the corresponding components of the n-type devices. Some of the processing steps are common to both the p-type devices and the n-type devices, but many steps are not common and thus need to be performed separately by masking the area for one type of device while processing the other type of device. For example, the p-type and n-type devices require different well implantation, different gate polysilicon implantation, and different source and drain implantation.
For common processing steps, the processing conditions are in general not optimal for either the p-type devices or for the n-type devices, but instead a compromise between the two different optimal conditions is made. For example, the stress of shallow trench isolation cannot be simultaneously optimized for both p-type devices and n-type devices since an optimal stress for a p-type metal-oxide-semiconductor field effect transistor (MOSFET) is compressive, while an optimal stress for an n-type MOSFET is tensile. The structure of a gate stack is another example in which different processes between the p-type and n-type devices can improve the performance of both types of MOSFETs.
A consequence of forming both types of semiconductor devices on the same level is the formation of a boundary area between the two types of devices. Due to a finite overlay tolerance of the block masks, the boundary area needs to be at least as wide as the overlay tolerance of the block masks. Since p-type devices and n-type devices need to be placed in proximity, the boundary area may occupy a substantial portion of the total semiconductor area in high performance CMOS circuits. Furthermore, requirements for inter-well isolation also increase the boundary area between the two types of semiconductor devices.
In general, one group of high performance CMOS devices requires using a particular type of material and processing steps, while another group of high performance CMOS devices require using a different type of material and processing steps. At the same time, the two groups of high performance CMOS devices need to be physically placed in close proximity to facilitate wiring and to reduce delay in signal propagation. Use of block masks not only increases the process complexity and cost, but also reduces the packing density due to the requirement for boundary areas between the two groups of devices.
Therefore, there exists a need for a novel semiconductor structure and methods of manufacturing the same in which a first group of CMOS devices are subjected to a first type of processing, while a second group of CMOS devices are subjected to a second type of processing without using block masks that mask one group of devices while exposing the other group.
Furthermore, there exists a need for a semiconductor structure and methods of manufacturing the same in which the two groups of semiconductor devices are placed in proximity and may be wired locally with minimal length wiring distances.